Continuous knowledge acquisition embedded devices based on novel nanotechnology synaptic emulators for enabling enhanced security in everyday life situations

Mobile devices are already permanent companions in our every day life. They can be good candidates to monitor our environment, track our habits, and detect novel unforeseen situations to trigger alarm signals. However, this would require intensive and continuous computations, impossible to perform with today's technological solutions without discharging the batteries of our mobile devices in a few minutes. Here we propose to exploit learning systems with novel nano-scale learning devices, that result in ultra low power and very high density microchips, capable of performing powerful cognitive tasks, like detecting novelty within routine habits. In present days, Neuroscience is achieving an unprecedent rate of continuous discoveries, unvealing many intrigue details on how the brain learns profound cognitive meanings from continuous sensory data. Computational Neuroscience is the field which tries to understand the computing principles within the brain by developing software programs that follow the internal brain operations, as discovered in biological Neuroscience. The field of Neuromorphic Engineering, is a recent Engineering discipline that tries to exploit neuroscience and computational neuroscience discoveries, by building real physical hardware device that compute based on the same principles. One key computational aspect in Neuroscience is the representation of information by a flow of neural spikes. Biological sensors (eyes, ears, olfaction, etc), all generate flows of spikes that feed areas of the brain. The brain itself interchanges spikes within the neurons, by communicating them through massively connected synapses. Synapses modulate their efficacies as a function of these flows of spikes, resulting in learned representations of the information transmitted. Neuromorphic Engineers build hardware systems mimicking these functionalites. In recent years, an impressive boom in exploiting neurocomputational principles on man-made systems is taking place. Big companies, like IBM and Google are investing heavily in achieving large computing facilities exploiting neurocomputational knowledge. On the other side, Nanotechnolies are also progressing quite rapidly in recent years. Resistive RAM nanodevices are already an industrial reality. These are tiny devices, with size in the range of tens of nano meters, that behave as resistances of varying magnitude. These devices, if properly connected to neuron emulating circuits within a chips, can be used to emulate neural tissue with millions of neurons and billions of synapses within one single chip, consuming micro watts of power. The applying group of this proposal is an experienced group in neuromorphic engineering, with an important international track record over the past 20 years in the field. The group is very well connected to the main players in europe developing the latest RRAM devices, and has an excellent background knowledge for providing a roadmap to exploit such novel technology in real practical mobile systems. In the present proposal we intend to perform a step forward by developing a proof-of-concept prototype chip based on RRAM devices and spiking silicon neurons that can perform some kind of cognitive learning and adaptation task with the goal of detecting novelty within routine environmental scenarios.

Bernabe Linares Barranco
Bernabe Linares Barranco

Bernabé Linares-Barranco has been involved with circuit design for telecommunication circuits, VLSI emulators of biological neurons, VLSI neural based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, and VLSI transistor mismatch parameters characterization.

Dr. Linares-Barranco was co-recipient of the 1997 IEEE Transactions on VLSI Systems Best Paper Award for the paper "A Real-Time Clustering Microchip Neural Engine", and of the 2000 IEEE Transactions on Circuits and Systems Darlington Award for the paper "A General Translinear Principle for Subthreshold MOS Transistors".

Since April 2010 he is Associate Editor for the new journal "Frontiers in Neuromorphic Engineering", as part of the open access "Frontiers in Neuroscience" journal series ( He is co-author of the book "Adaptive Resonance Theory Microchips ". He was Chief Guest Editor of the IEEE Transactions on Neural Networks Special Issue on 'Hardware Neural Networks Implementations '. He is an IEEE Fellow since January 2010.

Charanraj Mohan
Charanraj Mohan

Charanraj Mohan did his Bachelors' degree in electrical and electronics engineering under affiliated institution of Anna University, India. He is the recipient of HERITAGE (Europe-India partnership)- Erasmus Mundus fellowship for his Masters' in electronics, communication & signal processing at University of Seville, Spain. Presently, he is with the neuromorphic group at Institute of Microelectronics, Seville, Spain. His area of interest includes sub-micron technology circuit design and memristive device applications

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